- 08 Jun, 2020 1 commit
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Martin Jäger authored
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- 08 May, 2020 1 commit
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Martin Jäger authored
- Add BAT+/- and EXT+/- markings to terminals (#2) - Change C30 to 470nF (#5) - Add C20 (47nF) at VC0 pin (#5) - Add C21 and R72 for proper low-pass filter of VDD (#5) - Change C39 at VREF to 1uF (#5) - Add R70: Pull-down for PCHG FET (#5) - Add R73: Weak pull-down for 5V supply (#6)
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- 12 Aug, 2019 2 commits
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Martin Jaeger authored
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Martin Jaeger authored
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